• DocumentCode
    1340794
  • Title

    Forward body-bias MOS (FBMOS) dual rail logic using an adiabatic charging technique with sub -0.6 V operation

  • Author

    Kioi, K. ; Kotaki, H. ; Kakimoto, S. ; Fukushima, T. ; Sato, Y.

  • Author_Institution
    Central Res. Labs., Sharp Corp., Nara, Japan
  • Volume
    33
  • Issue
    14
  • fYear
    1997
  • fDate
    7/3/1997 12:00:00 AM
  • Firstpage
    1200
  • Lastpage
    1201
  • Abstract
    A novel logic family for low-voltage adiabatic logic, called forward body-bias MOS (FBMOS) dual rail logic, has been proposed. This technique uses forward body-bias effects to enable non-floating output levels during the entire data valid time without increased transistor count
  • Keywords
    CMOS logic circuits; logic design; logic gates; -0.6 V; 0.25 mum; LV logic family; adiabatic charging technique; dual rail logic; forward body-bias MOS logic; low-voltage adiabatic logic; nonfloating output levels; twin double-well CMOS process;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970810
  • Filename
    603568
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1340794