Title :
Logical modelling of delay degradation effect in static CMOS gates
Author :
Bellido-Diaz, M.J. ; Juan-Chico, J. ; Acosta, A.J. ; Valencia, M. ; Huertas, J.L.
Author_Institution :
Dept. de Disefio de Circuitos Digitales, Inst. de Microelectronica de Sevilla, Spain
fDate :
4/1/2000 12:00:00 AM
Abstract :
A delay model for static CMOS gates with application in gate level logic simulation is presented. It incorporates the degradation effect on narrow pulses and is named PID (pure, inertial and degradation). The results lead to the conclusion that the proposed new delay model maintains the high speed of gate-level logic simulation with a precision comparable to that of electrical simulation
Keywords :
CMOS logic circuits; delay degradation effect; delay model; gate level logic simulation; gate-level logic simulation; logical modelling; static CMOS gates;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:20000197
