High-Speed Transistorized Adder for a Digital Computer

An adder is described that has been developed for the Floating Indexed Point Arithmetic Unit, FLIP, to be used in conjunction with GEORGE, the existing computer built at Argonne National Laboratory. The logic of the high-speed adder and the special circuits required are presented. The adder is parallel and its high speed is made possible by reducing the carry propagation time. Each bit of the adder contributes one transistor to make up a tall AND gate which reduces the carry propagation time to 0.2 ¿sec. Using this high-speed carry propagation and rather common RCTL transistor circuitry, it is possible to complete an addition in less than 0.25 ¿sec.