Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer

Author

Sitthimahachaikul, Nattapol ; Rao, Lakshmi P. ; Hurst, Paul J.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA

Volume

59

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

652

Lastpage

663

Abstract

In a conventional analog adaptive forward equalizer (FE), parasitic capacitance introduces an undesired RC pole at the output node of the equalizer. At high data rates, this pole can introduce intersymbol interference (ISI) that degrades performance. This paper considers the effect of the parasitic pole and presents two approaches to deal with the parasitic pole. The first approach uses an extra tap in the FE; the second uses chopping. Also, the filtered-x LMS (FX-LMS) algorithm is used to allow the equalizer to adapt and correct for the parasitic pole. Implementations of the FX-LMS algorithm and the chopper technique are presented. The conventional and new architectures and various adaptation algorithms are compared via simulation.

Keywords

adaptive equalisers; capacitance; intersymbol interference; RC pole; adaptation algorithm; analog adaptive forward equalizer; analog equalizer; chopper technique; filtered-x LMS algorithm; high data rates; intersymbol interference; parasitic capacitance; summation-node parasitic pole; Capacitance; Decision feedback equalizers; Equations; Finite impulse response filter; Iron; Least squares approximation; Analog FIR equalizer; chopping; filtered-x LMS (FX-LMS) adaptation algorithm; parasitic capacitance;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2011.2165419

Filename

6035746