High-Speed Shift Registers Using One Core Per Bit

A three, and a two winding per core, high-speed, current driven, one core per bit shift register is presented together with an analysis of the basic circuit involved. An intermediate storage capacitor is used between successive logical elements. The charge and discharge of this capacitor are controlled in a positive manner by voltage blocking pulses. The undesired feedback of energy from one stage to earlier stages is thereby prevented, giving high efficiency of operation. The three winding per core register described is reversible and capable of operating in the megacycle range. The application of the basic shift register element to computer logic applications is described.