Controlling plasma charge damage in advanced semiconductor manufacturing. Challenge of small feature size device, large chip size, and large wafer size

During the ion implantation and plasma processing steps in IC manufacturing, the magnitude of charge damage on IC devices is often not as severe as the conventional charge damage antenna test structure estimate. On the other hand, the magnitude of the charge damage on the particular IC devices are often much more severe than the prediction of conventional antenna theory. Based on the new CMOS transistor and capacitor test structures (Spider´s SPIDER) which closely simulates actual IC circuit interconnections, it can be found that the conductor lines (antennas) connected to the source, drain, and substrate affect the damage magnitude of the MOS gate significantly. This suggests that to have effective control on the plasma charge damage in the advanced semiconductor manufacturing, the antenna must be connected to the MOS transistor gate, also the interactions of the antennas connected to the source, drain, and substrate to the gate antenna have to be considered. Depending on the relative direction, distance, and size of the antennas connected to the gate, source, drain, and substrate, the magnitude of the charge-damage effects can he enhanced or exacerbated. Furthermore, to predict and automatically warn the potential charge-damage during the phase of IC layout design, a new charge antenna Design Rule Check (DRC) software has been developed to perform systematic layout checking with the consideration of the interactions of the ULSI interconnection lines, which become antennas connected to all four terminals of MOS transistors