DocumentCode
1341303
Title
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers
Author
Huang, Yu-Jen ; Li, Jin-Fu
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Volume
20
Issue
11
fYear
2012
Firstpage
2123
Lastpage
2127
Abstract
This paper proposes an enhanced IEEE 1500 test wrapper to support the testing and diagnosis of the single-port or multi-port RAM core attached to the enhanced IEEE 1500 test wrapper without incurring large area overhead to small memories. Effective test time reduction techniques for the proposed test scheme are also proposed. Simulation results show that the additional area cost for implementing the enhanced IEEE 1500 test wrapper is only about 0.58% for a 64 K-bit single-port RAM and only 0.57% for a 64 K-bit two-port RAM in 90-nm technology.
Keywords
IEEE standards; built-in self test; integrated circuit testing; random-access storage; system-on-chip; SOC; enhanced IEEE 1500 test wrappers; low-cost self-test technique; multiport RAM core; single-port RAM core; small RAM; Built-in self-test; Random access memory; System-on-a-chip; IEEE 1500; built-in self-test (BIST); multi-port RAM; random access memory (RAM); system-on-chip (SOC);
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2011.2165568
Filename
6035755
Link To Document