Title :
Architectural optimization for low-power nonpipelined asynchronous systems
Author :
Plana, Luis A. ; Nowick, Steven M.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
fDate :
3/1/1998 12:00:00 AM
Abstract :
This paper presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4.
Keywords :
SPICE; asynchronous circuits; circuit optimisation; logic design; SPICE simulation; architectural optimization; data hazard; dual-rail datapath; interlock; low-power asynchronous system; nonpipelined computation; sequencing controller; single-rail datapath; throughput; voltage scaling; Asynchronous circuits; Clocks; Concurrent computing; Control systems; Energy consumption; Hazards; SPICE; Throughput; Very large scale integration; Voltage;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
