A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

Author

Narasimham, Balaji ; Chandrasekharan, Karthik ; Liu, Zeke ; Wang, Jung K. ; Djaja, Gregory ; Gaspard, Nelson J. ; Kauppila, Jeffrey S. ; Bhuva, Bharat L.

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

59

Issue

6

fYear

2012

Firstpage

2847

Lastpage

2851

Abstract

A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14× and 3× improvements in the alpha and neutron SER, respectively, compared with a standard DFF.

Keywords

CMOS logic circuits; alpha-particle effects; flip-flops; hysteresis; integrated circuit layout; ion beam effects; logic design; neutron effects; performance evaluation; radiation hardening (electronics); CMOS process; DICE FF; alpha SER; alpha beams; heavy-ion beams; hysteresis DFF; hysteresis-based D-flip-flop design; improved SER hardness; layout-aware sensitive area simulations; low performance overhead; neutron SER; neutron beams; single-event hardness; size 28 nm; standard DFF; standard HDFF; test chip; Alpha particles; Flip-flops; Hysteresis; Neutrons; Single event upset; Alpha particles; SER; flip-flop; hardening-by-design; heavy-ions; hysteresis; latch; neutrons; single event; soft error;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2012.2223762

Filename

6365409