Fast fault translation

Test generator algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.