DocumentCode :
1342284
Title :
Timed state space exploration using POSETs
Author :
Belluomini, Wendy ; Myers, Chris J.
Author_Institution :
Res. Lab., IBM Corp., Austin, TX, USA
Volume :
19
Issue :
5
fYear :
2000
fDate :
5/1/2000 12:00:00 AM
Firstpage :
501
Lastpage :
520
Abstract :
This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSET´s) to minimize the number of regions necessary. This algorithm operates on specifications sufficiently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing significant improvement in runtime and memory usage
Keywords :
asynchronous circuits; computational complexity; formal verification; logic CAD; set theory; state-space methods; timing; POSETs; computational complexity; geometric regions; memory usage; partially ordered sets; runtime; timed state space exploration; timing analysis algorithm; Asynchronous circuits; Boolean functions; Circuit synthesis; Clocks; Explosions; Interleaved codes; Logic circuits; Space exploration; State-space methods; Timing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.845076
Filename :
845076
Link To Document :
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