Title :
STBM: a fast algorithm to simulate IDDQ tests for leakage faults
Author :
Chakravarty, Sreejit ; Zachariah, Sujit Thomas
Author_Institution :
Test Technol., Intel Corp., Santa Clara, CA, USA
fDate :
5/1/2000 12:00:00 AM
Abstract :
State-transition-based method (STBM), a fast algorithm for computing leakage fault coverage of IDDQ tests and selecting optimal IDDQ measurement points, targeting leakage faults, is presented. Experimental results presented show that STBM outperforms all known algorithms for the same problems. A comparative study of leakage and pseudo-stuck-at fault models, the latter used by commercial tool vendors, show that the pseudo-stuck-at coverage values are very pessimistic
Keywords :
CMOS digital integrated circuits; digital simulation; electronic engineering computing; fault simulation; integrated circuit testing; leakage currents; logic testing; IDDQ tests simulation; STBM algorithm; fast algorithm; fault currents; leakage faults; optimal IDDQ measurement points selection; state-transition-based method; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Fault currents; Fault diagnosis; Logic testing; Microprocessors; Semiconductor device testing; Sequential circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
