Design for Soft Error Resiliency in Internet Core Routers

This paper describes the modeling, analysis and verification methods used to achieve a reliability target set for transient outages in equipment used to build the backbone routing infrastructure of the Internet. We focus on the ASIC design and analysis techniques that were undertaken to achieve the targeted behavior using 65 nm technology. Considerable attention was paid to Single Event Upset in flip-flops and their potential to produce network impacting events that are not systematically detected and controlled. Using random fault injection in large scale RTL simulations, and slack time distributions from static timing analysis, estimates of functional and temporal soft error masking effects were applied to a system soft error model to drive decisions on interventions such as the use of larger resilient flip-flops, parity protection of registers groupings, and designed responses to detected upsets.