Title :
Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching
Author :
Fong, Xuanyao ; Choday, Sri Harsha ; Roy, Kaushik
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Green´s Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16 nm predictive technology.
Keywords :
Green´s function methods; MRAM devices; magnetic tunnelling; optimisation; random-access storage; silicon-on-insulator; switching; transistors; Landau-Lifshitz-Gilbert equation; Slonczewski spin-torque; Verilog-A model; bit-cell level optimization; magnetic random access memory; magnetic tunnel junction; magnetization dynamics; mixed-mode simulation framework; nonequilibrium Greens function method; nonvolatile memory; self-consistency; silicon-on-insulator CMOS technology; size 45 nm; spin-transfer torque switching; transistor sizing; Current density; Magnetic tunneling; Mathematical model; Optimization; Resistance; Switches; Torque; Circuit optimization; magnetic memories; magnetic tunnel junctions (MTJ); memory architectures; spin-transfer torque MRAM (STT-MRAM) bit-cells;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2011.2169456