A Unified Availability Analysis Method for Systems Containing Design Errors

This paper gives a unified approach to modeling digital structures and accounts for i) the hardware failure process and ii) the failure process due to design errors. The instantaneous unavailability, always larger than the value resulting from the hardware performance, shows an appreciable peak with respect to its asymptotic value whose height and length are functions of the failure rates associated with the different design errors. An approximate value for the maximum of this peak is given which, under certain conditions, can be used as a more realistic figure for unavailability than the asymptotic value usually considered.