Title :
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"
Author :
Sung, Ki-Hyuk ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
6/1/2000 12:00:00 AM
Abstract :
For the original paper see ibid., vol. 33, no. 10, p. 1568-1571 (1998). In the aforementioned paper a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang et al. It is claimed by the commenters that the proposed flip-flop violates the edge-triggering characteristic. However, it is shown that high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler.
Keywords :
CMOS digital integrated circuits; delays; flip-flops; high-speed integrated circuits; prescalers; TSPC ratioed D-flip-flop; dynamic flip-flops; edge-triggering characteristic; high clock frequency; high-speed dual-modulus prescaler; propagation delay; true single-phase clocking; Clocks; Counting circuits; Equivalent circuits; Flip-flops; Frequency; Inverters; MOSFETs; Propagation delay; Short circuit currents; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
