Title :
A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
Author :
Jahinuzzaman, Shah M. ; Rennie, David J. ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada
Abstract :
We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit noise; leakage currents; neutron effects; nuclear electronics; CMOS technology; DICE SRAM cell; accelerated neutron radiation tests; differential read operation; dual interlocked cell SRAM cell; leakage current; noise margin; quad-node ten transistor; robust sensing; size 90 nm; soft error rate; CMOS technology; Error analysis; Error correction codes; Latches; MIM capacitors; Neutrons; Noise robustness; Random access memory; Single event upset; Voltage; Differential read; SRAMs; single event effects; soft error rates; standard process;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2009.2032090
