• DocumentCode
    1342961
  • Title

    Parallel pipelined histogram architectures

  • Author

    Cadenas, J. ; Sherratt, R. ; Huerta, P.

  • Author_Institution
    Sch. of Syst. Eng., Univ. of Reading, Reading, UK
  • Volume
    47
  • Issue
    20
  • fYear
    2011
  • Firstpage
    1118
  • Lastpage
    1120
  • Abstract
    Proposed is a unique cell histogram architecture which will process k data items in parallel to compute 2q histogram bins per time step. An array of m/2q cells computes an m-bin histogram with a speed-up factor of k; k≥2 makes it faster than current dual-ported memory implementations. Furthermore, simple mechanisms for conflict-free storing of the histogram bins into an external memory array are discussed.
  • Keywords
    digital storage; parallel processing; pipeline processing; 2q histogram; cell histogram architecture; external memory array; parallel pipelined histogram architectures;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2011.2390
  • Filename
    6036052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1342961