5 GHz low power frequency synthesiser with dual-modulus counter

A 5 GHz low power frequency synthesiser with a dual-modulus counter (DMC) was fabricated in 0.18 m CMOS technology. The DMC allows to reduce the power consumption and to provide the functionality of the divider without a swallower counter. The settling time takes no more than 5 s with an adaptive bandwidth topology. The measured phase noise is 87 dBc/Hz and 119 dBc/Hz at 10 kHz and 1 MHz offset frequencies, respectively. The reference spurs level is lower than 55 dBc at 10 MHz offset. The proposed synthesiser covers frequencies between 5.14 and 5.86 GHz in steps of 20 MHz and consumes 16.4 mW at 1.5 V supply voltage.