• DocumentCode
    1343549
  • Title

    ESD Engineering Fully Silicided Large MOSFET Driver for Maximum It\\hbox {1} Performance

  • Author

    Iyer, Natarajan Mahadeva ; Hao, Jiang ; Kiong, Yap Hin ; Guowei, Zhang ; Wang, Xiaoping ; Verma, Purakh Raj

  • Author_Institution
    GLOBALFOUNDRIES, Singapore, Singapore
  • Volume
    11
  • Issue
    4
  • fYear
    2011
  • Firstpage
    516
  • Lastpage
    521
  • Abstract
    Simultaneous optimization of LDD and antipunch-through implant conditions for ESD performance of very large width silicided output driver NMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulsewidth, are detailed.
  • Keywords
    MOSFET; circuit optimisation; driver circuits; electrostatic discharge; ESD engineering fully silicided large MOSFET driver; TLP pulsewidth; antipunch-through implant conditions; device sensitivity; pulse rise time; Electrostatic discharge; Logic gates; MOSFETs; Optimization; Performance evaluation; Semiconductor optical amplifiers; Antipunchthrough (APT) implant; electrostatic discharge; nonsnapback operation; power driver array optimization; process optimization;
  • fLanguage
    English
  • Journal_Title
    Device and Materials Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1530-4388
  • Type

    jour

  • DOI
    10.1109/TDMR.2011.2171345
  • Filename
    6036163
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1343549