Title :
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery
Author :
Yamaguchi, Koichi ; Hori, Yoshihiko ; Nakajima, Keiichi ; Suzuki, Kazumasa ; Mizuno, Masayuki ; Hayama, Hiroshi
Author_Institution :
Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan
Abstract :
A 2.0 Gb/s clock-embedded interface for LCD drivers, Advanced-PPmL¿, has been developed for high-speed data transfer and reduced area in transmission media. Only one pair of differential signals is needed to control the LCD driver and to display images. A newly developed 1/5-rate phase frequency detector helps achieve a 25% power reduction compared with a half-rate architecture. Pulse filtering of phase control signals and a 4B5B-based interface protocol have been developed for noise-tolerant clock recovery. Power consumption in the clock and data recovery (CDR) is 93 mW with a 3.0 V supply. The rms jitter in the recovered clock is 11 ps when a PRBS7 pattern is used.
Keywords :
driver circuits; jitter; liquid crystal displays; synchronisation; 1/5-rate noise-tolerant phase; 1/5-rate phase frequency detector; 4B5B-based interface protocol; advanced-PPmL; bit rate 2.0 Gbit/s; clock and data recovery; clock-embedded interface; frequency 120 Hz; frequency recovery; full-HD LCD drivers; high-speed data transfer; image display; noise-tolerant clock recovery; phase control signals; power consumption; pulse filtering; transmission media; voltage 3.0 V; Clocks; Control systems; Degradation; Frequency; Jitter; Liquid crystal displays; National electric code; Noise reduction; Phase noise; Timing; Clock and data recovery; LCD driver; clock-embedded interface; frequency detector; jitter;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2031024
