An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

Author

Gatta, Francesco ; Gomez, Ray ; Shin, Young J. ; Hayashi, Takayuki ; Zou, Hanli ; Chang, James Y C ; Dauphinee, Leonard ; Xiao, Jianhong ; Chang, Dave S -H ; Chih, Tai-Hong ; Brandolini, Massimo ; Koh, Dongsoo ; Hung, Bryan Juo-Jung ; Wu, Tao ; Introini,

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

44

Issue

12

fYear

2009

Firstpage

3511

Lastpage

3525

Abstract

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

Keywords

CMOS digital integrated circuits; UHF circuits; cable television; circuit tuning; embedded systems; phase locked loops; system-on-chip; DOCSIS 3.0 system-on-a chip; bit rate 320 Mbit/s; bit rate 400 Mbit/s; data-over-cable service interface specification standard; digital image rejection; embedded CMOS digital dual tuner; frequency 48 MHz to 1 GHz; frequency 8 MHz; harmonic rejection front-end; low-noise high-frequency resolution PLL; multichannel broadband tuner; phase-locked loop; set-top box; size 65 nm; stringent SCTE 40 specification; Bandwidth; Baseband; CMOS technology; Cable TV; Modems; Phase locked loops; Power harmonic filters; Quadrature amplitude modulation; Signal to noise ratio; Tuners; 256 QAM; 64 QAM; ACI; ADC; Annex A; Annex B; CATV tuners; CMOS; CSO; CTB; DAC; DC offset loops; DOCSIS 3.0; SCTE40; SOC; baseband IQ; cable modem; direct digital frequency synthesizer (DDFS); down-stream channels (DS); downstream power management (DPM); harmonic rejection RF front-end (HR RFFE); image rejection; local oscillator (LO); low IF; noise figure (NF); set-top box; signal-to-noise ratio (SNR); variable-gain amplifier (VGA); variable-gain low-noise amplifier (VGLNA);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2032497

Filename

5342363