Title :
A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method
Author :
Xing, Nan ; Woo, Jong-Kwan ; Shin, Woo-Yeol ; Lee, Hyunjoong ; Kim, Suhwan
Author_Institution :
Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 μm CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.
Keywords :
CMOS integrated circuits; delay lock loops; voltage-controlled oscillators; CMOS process; cyclic Vernier delay line; dynamic range; fractional difference conversion method; fractional difference conversion scheme; input-range cyclic time-to-digital converter; negative feedbacks; power 6.4 mW; time 14.6 ps; time 50 ns; two delay locked loops; Delay lines; Dynamic range; Negative feedback; Propagation delay; Tracking loops; Voltage-controlled oscillators; Delay-locked loop (DLL); fractional conversion scheme; input range; resolution; time-to-digital converter (TDC); triggerable voltage controlled oscillator (TVCO);
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2010.2073810
