DocumentCode :
1343729
Title :
A 12 bit 2.9 GS/s DAC With IM3 
60 dBc Beyond 1 GHz in 65 nm CMOS
Author :
Lin, Chi-Hung ; Van der Goes, Frank M L ; Westra, Jan R. ; Mulder, Jan ; Lin, Yu ; Arslan, Erol ; Ayranci, Emre ; Liu, Xiaodong ; Bult, Klaas
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Volume :
44
Issue :
12
fYear :
2009
Firstpage :
3285
Lastpage :
3293
Abstract :
A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < ¿-60 dBc beyond 1 GHz while driving a 50 ¿ load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with ¿always-ON¿ biasing.
Keywords :
CMOS digital integrated circuits; digital-analogue conversion; CMOS; always-ON biasing; digital-to-analog converter; power 188 mW; resistance 50 ohm; size 65 nm; voltage 2.5 V; Decoding; Digital signal processing; Digital-analog conversion; Digital-to-frequency converters; Frequency conversion; Impedance; Joining processes; Limiting; Linearity; Signal sampling; CMOS; D/A converters; HD3; IM3; current-steering; digital-to-analog converter (DAC); full Nyquist; high frequency; high speed;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2032624
Filename :
5342368
Link To Document :
