Title :
Novel 3-D Coaxial Interconnect System for Use in System-in-Package Applications
Author :
LaMeres, Brock J. ; McIntosh, Christopher ; Abusultan, Monther
Author_Institution :
Dept. of Electr. & Comput. Eng., Montana State Univ., Bozeman, MT, USA
Abstract :
This paper presents the design and demonstration of a novel die-to-die interconnect system for deployment in system-in-package (SiP) applications with adjacent or stacked-die configurations. The interconnect system consists of miniature coaxial cables that are mounted to a standard Silicon substrate using an etched trench along the perimeter of the die. The trench serves as a self-alignment feature for both the signal and ground contacts in addition to providing mechanical strain relief for the coaxial cable. The system is designed to interface on-chip coplanar transmission lines to off-chip coaxial transmission lines to produce a fully impedance matched system. This approach promises to dramatically improve the electrical performance of high-speed, die-to-die signals by eliminating impedance discontinuities, providing a shielded signal path, and providing a low-impedance return path for the switching signal. The new interconnect system is designed to be selectively added to a standard wire bond pad configuration using an incremental etching process. This paper describes the design process for the new approach including the fabrication sequence to create the transition trenches. Finite-element analysis is performed to evaluate the electrical performance of the proposed system.
Keywords :
coaxial cables; coplanar transmission lines; finite element analysis; integrated circuit interconnections; isolation technology; system-in-package; 3D coaxial interconnect system; adjacent die configuration; die-to-die interconnect system; finite-element analysis; mechanical strain relief; miniature coaxial cables; off-chip coaxial transmission lines; on-chip coplanar transmission lines; return path; shielded signal path; stacked-die configuration; system-in-package; wire bond pad configuration; Integrated circuit (IC) packaging; simultaneous switching noise (SSN); system-in-package (SiP); three-dimensional (3-D) chip stacking;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2009.2033942