DocumentCode :
1344209
Title :
Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector
Author :
Britton, C.L., Jr. ; Bryan, W.L. ; Emery, M.S. ; Ericson, M.N. ; Musrock, M.S. ; Simpson, M.L. ; Smith, M.C. ; Walker, J.W. ; Wintenberg, A.L. ; Young, G.R. ; Allen, M.D. ; Clonts, L.G. ; Jones, R.L. ; Kennedy, E.J. ; Smith, R.S. ; Boissevain, J. ; Jacak,
Author_Institution :
Oak Ridge Nat. Lab., TN, USA
Volume :
44
Issue :
3
fYear :
1997
fDate :
6/1/1997 12:00:00 AM
Firstpage :
283
Lastpage :
288
Abstract :
The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 μs ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 μm n-well CMOS process used for preamplifier fabrication
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; detector circuits; discriminators; mixed analogue-digital integrated circuits; multichip modules; nuclear electronics; position sensitive particle detectors; preamplifiers; radiation hardening (electronics); silicon radiation detectors; timing circuits; 1.2 mum; 5 mus; ADC; CMOS process; Heap Manager; Multiplicity Vertex Detector; PHENIX; analog memory; beam test electronics; current-mode summed multiplicity discriminator; data buffering; data formatting; ionizing radiation damage; multi-chip module; post-memory analog correlator; preamplifier; preamplifier-gain stage; timing control; Analog memory; Circuit testing; Collaboration; Colliding beam devices; Correlators; Detectors; Electronic equipment testing; Signal processing; System testing; Timing;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.603657
Filename :
603657
Link To Document :
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