Data Retention and Program/Erase Sensitivity to the Array Background Pattern in Deca-nanometer nand Flash Memories

This paper presents a new cell crosstalk effect in deca-nanometer nand Flash memories, making the data retention and erase transients of fresh cells dependent on the threshold-voltage level at which adjacent cells in the array are placed. In particular, a programmed cell is shown to display a larger threshold-voltage loss when its adjacent cells are in the erased than in the programmed state, with cells on the same bit line and word line having a similar impact on the acceleration of the threshold-voltage loss. The effect is explained by means of 3-D TCAD simulations, showing that a low threshold voltage for the adjacent cells increases the discharging tunneling current of the monitored cell for a fixed negative potential of its floating gate. This is due to a change of the electric field profile at the corners of the monitored cell active area when the potential of the floating gate of its neighboring cells is modified.