Title :
A method for increasing the IDDQ testability
Author :
Dalpasso, Marcello ; Favalli, Michele
Author_Institution :
Dipt. di Ingegneria, Ferrara Univ., Italy
fDate :
10/1/1997 12:00:00 AM
Abstract :
At different design levels, testability is becoming more and more important since high levels of reliability are required by many applications. In this work, a novel approach to the mapping between signal lines and gate inputs is proposed, targeting the IDDQ testability of internal faults. Suggesting an additional cost function for the routing process, the method provides significant testability enhancements without affecting either the gate-level structure of the circuit or the internal layout of the gates, as proved with regards to bridging faults
Keywords :
CMOS logic circuits; design for testability; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic testing; CMOS logic; IDDQ testability; bridging faults; cost function; gate inputs; gate-level structure; internal faults; internal layout; mapping; reliability; signal lines; Benchmark testing; Circuit faults; Circuit testing; Cost function; Electrical fault detection; Fault detection; Integrated circuit testing; Logic design; Logic testing; Routing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
