Title :
On the reconfiguration of degradable VLSI/WSI arrays
Author :
Low, C.P. ; Leong, H.W.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
fDate :
10/1/1997 12:00:00 AM
Abstract :
This paper consider the problem of reconfiguring two dimensional very large scale integration (VLSI/WSI) arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, we show that a special case of the reconfiguration problem with row bypass and column rerouting capabilities is optimally solvable in linear time. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays
Keywords :
VLSI; cellular arrays; computational complexity; integrated circuit reliability; integrated memory circuits; logic arrays; network routing; wafer-scale integration; 2D arrays; NP-complete problem; column rerouting capabilities; defective host array; degradable VLSI/WSI arrays; fault-free subarray; reconfiguration algorithm; routing constraints; row bypass capabilities; switching constraints; two dimensional arrays; Circuit faults; Costs; Degradation; Fabrication; Fault tolerance; Greedy algorithms; Random access memory; Redundancy; Routing; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on