Bus in a new light

Author

Aloisio, A. ; Cevenini, F. ; Fiore, D.J.

Author_Institution

Dipartimento di Sci. Fisiche, Naples Univ., Italy

Volume

47

Issue

2

fYear

2000

fDate

4/1/2000 12:00:00 AM

Firstpage

309

Lastpage

312

Abstract

We describe a parallel optical link based on the Siemens´ PAROLI DC chip-set-a 22-bit optical parallel bus. A companion link controller has been designed around Xilinx FPGAs, in order to transmit 32-bit data plus 4-bit flags at 40 MHz with parity check. The FPGA design handles the user payload at 40 MHz and performs segmentation and reassembly at 200 MHz. In this work, emphasis is put on the FPGA interface to the Siemens´ chip-set-a design which puts to the proof the FPGA architecture. We also present POLAR (Parallel Optical Link Architecture), a VME board which implements a full duplex parallel optical link using this structure: bus in a new light

Keywords

field programmable gate arrays; optical communication; optical links; parallel architectures; system buses; 200 MHz; 32 bit; FPGA design; PAROLI DC chip-set; POLAR; Parallel Optical Link Architecture; Siemens; VME board; Xilinx FPGA; companion link controller; full duplex parallel optical link; optical parallel bus; parallel optical link; parity check; reassembly; user payload; Clocks; Computer architecture; Data acquisition; Field programmable gate arrays; High speed optical techniques; Optical arrays; Optical crosstalk; Optical fiber communication; Optical transmitters; Vertical cavity surface emitting lasers;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.846170

Filename

846170