Planarized multilevel interconnection using chemical mechanical polishing of selective CVD-Al via plugs

Author

Amazawa, Takao ; Yamamoto, Eiichi ; Arita, Yoshinobu

Author_Institution

NTT Syst. Electron. Labs., Kanagawa, Japan

Volume

45

Issue

4

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

815

Lastpage

820

Abstract

A planarization process for selective CVD-Al via plugs using chemical mechanical polishing (CMP) is proposed and a four-level interconnection system with all stacked via plugs is demonstrated. A Cl ₂/Ar post-cleaning treatment after Al plug CMP is shown to be the key process in obtaining excellent via chain characteristics with high yield and small resistance scattering. A sandwich of Ti/TiN/Ti barrier layers with a CVD-Al plug is proved to be one of the best via plug structures because of its low via resistance and high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4-μm, equal pitch and four-level interconnection

Keywords

aluminium; electromigration; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; large scale integration; logic arrays; polishing; 1.4 micron; Al; chemical mechanical polishing; gate array LSIs; planarized multilevel interconnection; post-cleaning treatment; reliability; resistance scattering; selective CVD; stacked via plugs; via chain characteristics; via resistance; yield; Aluminum; Argon; Chemical processes; Chemical vapor deposition; Conducting materials; Inductors; Infrared heating; Integrated circuit interconnections; Planarization; Plugs;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.662782

Filename

662782