DocumentCode :
1345524
Title :
Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films
Author :
Lei, Tan Fu ; Cheng, Juing-Yi ; Shiau, Shyh Yin ; Chao, Tien Sheng ; Lai, Chao Sung
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
45
Issue :
4
fYear :
1998
fDate :
4/1/1998 12:00:00 AM
Firstpage :
912
Lastpage :
917
Abstract :
This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Qbd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides´ upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide
Keywords :
electric breakdown; electron traps; elemental semiconductors; leakage currents; oxidation; polishing; semiconductor thin films; semiconductor-insulator boundaries; silicon; silicon compounds; SiO2-Si; charge to breakdown; chemical mechanical polishing; dielectric breakdown field; electron barrier height; electron trapping rate; leakage current; planar surface morphology; polyoxide; polysilicon film; polysilicon oxide; thermal deposition; thermal growth; trapped charge density; Chaos; Dielectric breakdown; EPROM; Electron traps; Leakage current; Planarization; Rough surfaces; Silicon compounds; Surface morphology; Surface roughness;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.662802
Filename :
662802
Link To Document :
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