• DocumentCode
    1345604
  • Title

    Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-μm CMOS technology

  • Author

    Vuong, H.H. ; Eshraghi, S.A. ; Rafferty, C.S. ; Hillenius, S.J. ; Pinto, M.R. ; Diodato, P.W. ; Cong, H.-I. ; Zeitzoff, P.M.

  • Author_Institution
    Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
  • Volume
    45
  • Issue
    4
  • fYear
    1998
  • fDate
    4/1/1998 12:00:00 AM
  • Firstpage
    991
  • Lastpage
    993
  • Abstract
    TCAD tools were used to design and benchmark 0.25-μm buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages VDD>1.4 V, and for NOR gates with V DD>2.4 V
  • Keywords
    CMOS logic circuits; circuit CAD; delays; integrated circuit design; integrated circuit modelling; integrated circuit technology; logic gates; 0.25 micron; 1.4 V; 2.4 V; BCPMOS; NAND gates; NOR gates; SCPMOS; TCAD modelling; benchmarking; buried-channel PMOS; circuit performance; device performance; gate delays; invertor gates; submicron CMOS technology; surface-channel PMOS; CMOS technology; Circuit optimization; Delay; Design optimization; Implants; Inverters; Manufacturing processes; Semiconductor device modeling; Switches; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.662818
  • Filename
    662818
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1345604