DSP implementations of sophisticated speech codecs

Author

Taka, Masahiro ; Maruta, Rikio ; Unagami, Shigeyuki

Author_Institution

Transmission Syst. Labs., NTT, Kanagawa, Japan

Volume

6

Issue

2

fYear

1988

fDate

2/1/1988 12:00:00 AM

Firstpage

274

Lastpage

282

Abstract

Hardware implementation aspects of sophisticated speech codecs are addressed. The major points discussed are approaches to implementation of the sophisticated speech codecs, requirements for DSP (digital signal-processing) implementation of the codecs, such as the type of arithmetic processing and the necessity of bit-level specifications, and codec implementation and DSP programming techniques for three specific coding algorithms: 32-kb/s ADPCM (adaptive digital pulse code modulation), 64-kb/s (7 kHz) SB (subband)-ADPCM, and 16-kb/s APC-AB (adaptive predictive coding with adaptive but allocation) codecs

Keywords

codecs; computerised signal processing; pulse-code modulation; speech analysis and processing; 16 kbits/s; 32 kbits/s; 64 kbits/s; 7 kHz; ADPCM; DSP programming techniques; VLF; adaptive digital pulse code modulation; adaptive predictive coding with adaptive but allocation; arithmetic processing; bit-level specifications; codec implementation; digital signal-processing; speech codecs; Bit rate; Costs; Digital signal processing; Digital signal processors; Hardware; Large scale integration; Power generation economics; Signal processing algorithms; Speech codecs; Speech coding;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.604

Filename

604