Wafer level chip scale packaging (WL-CSP): an overview

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP´s when underfill is not used than for equivalent flip chip parts. Rambus^TM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages