Author :
Rinne, Glenn A. ; Walling, James D. ; Mis, J. Daniel
Author_Institution :
Unitive Electron. Inc., Res. Triangle Park, NC, USA
fDate :
5/1/2000 12:00:00 AM
Abstract :
A chip scale package (CSP) using wafer scale processing was developed for a line of low cost, small form factor integrated circuits. The package uses polymeric repassivation and electrodeposited solder bumps connected by a unique conductor patterning method. The finished package resembles a common chip resistor. Reliability testing was used to optimize the bump design and the assembly methodologies. Field performance of more than 20 million packages has validated the test results
Keywords :
chip scale packaging; flip-chip devices; integrated circuit reliability; soldering; conductor patterning method; direct chip attach; electrodeposited solder bumps; low cost; minimal chip scale package; polymeric repassivation; redistributed flip chip; reliability testing; small form factor integrated circuits; two-pin device; wafer scale processing; Assembly; Chip scale packaging; Circuit testing; Conductors; Costs; Design optimization; Integrated circuit packaging; Integrated circuit reliability; Polymers; Resistors;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/6040.846635
