A comprehensive submicrometer MOST delay model and its application to CMOS buffers

Author

Cocchini, Pasquale ; Piccinini, Gianluca ; Zamboni, Maurizio

Author_Institution

Dept. of Electron., Politecnico di Torino, Italy

Volume

32

Issue

8

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

1254

Lastpage

1262

Abstract

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits

Keywords

CMOS digital integrated circuits; MOSFET; SPICE; buffer circuits; circuit analysis computing; circuit optimisation; delays; integrated circuit modelling; semiconductor device models; 0.7 mum; CMOS reference technology; CMOS tapered buffers; MOS transistors; SPICE simulations; delay estimation; feedforward capacitive coupling; input voltage slope range; minimum inverter; optimization algorithms; propagation time; ramp shape input voltage; second-order effects; short-channel MOS transistors; submicrometer CMOS digital circuits; submicrometer MOST delay model; CMOS digital integrated circuits; CMOS technology; Coupling circuits; Delay; Digital circuits; MOSFETs; SPICE; Semiconductor device modeling; Shape; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.604081

Filename

604081