DocumentCode
1346076
Title
Ultrathin wafer level chip size package
Author
Badihi, Avner
Author_Institution
ShellCase Ltd., Jerusalem, Israel
Volume
23
Issue
2
fYear
2000
fDate
5/1/2000 12:00:00 AM
Firstpage
212
Lastpage
214
Abstract
The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP´s) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products
Keywords
chip scale packaging; encapsulation; ShellCase; Si; bumping; glass encapsulation; polymer layer; reliability; semiconductor wafer processing; wafer level chip size package; Electronics packaging; Encapsulation; Glass; Packaging machines; Protection; Semiconductor device packaging; Silicon; Solids; Surface-mount technology; Wafer scale integration;
fLanguage
English
Journal_Title
Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1521-3323
Type
jour
DOI
10.1109/6040.846636
Filename
846636
Link To Document