Microprocessor and LSI Microcircuit Reliability-Prediction Model

This paper discusses the development of an improved failure-rate prediction method which can be used to assess the reliability of complex and new-technology microcircuits, especially memories, microprocessors, and their support devices. The prediction models are similar to those presented in MIL-HDBK-217C with several modifications to reflect the variation of reliability sensitive parameters and to discriminate against the device design and usage attributes which contribute to known failure mechanisms. A comparison of the failure rate predictions calculated using MIL-HDBK-217C and the actual failure rates for LSI random logic and memory devices did not indicate a reasonable correlation. An analysis of the 217C models revealed that the lack of correlation was attributable to the generic consolidation of model parameters, which ultimately reduced model sensitivity to several critical reliability factors. The model accuracy was greatly improved, without substantially increasing model complexity, by separating some generic parameters into sets of more detailed parameters. The major model revisions included: ¿ Complexity factors oriented toward major device function and technology categories ¿ Development of temperature factors for each device technology, in both hermetic and nonhermetic packages ¿ Introduction of an additive package failure-rate factor based upon package type and number of functional pins ¿ Introduction of a voltage derating stress factor for CMOS devices with maximum recommended operating supply voltage greater than 12 volts ¿ Introduction of a ROM and PROM programming technique factor to reflect the influence of the programming mechanism used in these devices.