Title :
MicroSMD-a wafer level chip scale package
Author :
Kelkar, N. ; Mathew, R. ; Takiar, H. ; Nguyen, L.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
5/1/2000 12:00:00 AM
Abstract :
This paper outlines National Semiconductor´s concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability
Keywords :
chip scale packaging; integrated circuit reliability; surface mount technology; 0.5 mm; MicroSMD; National Semiconductor; board level assembly; bump pitch; interconnect reliability; low pin count analog devices; low pin count wireless devices; package construction; package reliability; process flow; qualification; wafer level chip scale package; Assembly; Chip scale packaging; Costs; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit reliability; Packaging machines; Protection; Semiconductor device packaging; Wafer scale integration;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/6040.846639
