Title :
Wafer-level chip size package (WL-CSP)
Author :
Töpper, Michael ; Fehlberg, Simone ; Scherpinski, Katrin ; Karduck, Claudia ; Glaw, Veronika ; Heinricht, Katrin ; Coskina, Paradiso ; Ehrmann, Oswin ; Reichl, Herbert
Author_Institution :
Fraunhofer Inst. of Reliability & Microintegration, Berlin, Germany
fDate :
5/1/2000 12:00:00 AM
Abstract :
Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost
Keywords :
chip scale packaging; integrated circuit design; integrated circuit reliability; WL-CSP; board technology; electronic systems; functionality; optimal product design; reliability; size reduction; total cost; wafer-level chip size package; Assembly; Chip scale packaging; Electronics packaging; Integrated circuit packaging; Integrated circuit technology; Plastic packaging; Printed circuits; Production; Semiconductor device packaging; Wafer scale integration;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/6040.846640
