Title :
A low-power CMOS analog vector quantizer
Author :
Cauwenberghs, Gert ; Pedroni, Volnei
Author_Institution :
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
fDate :
8/1/1997 12:00:00 AM
Abstract :
We present a parallel analog vector quantizer (VQ) in 2.0-μm double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16×16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic template storage measures 60×78 μm2. The output code is produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-decay product, independent of input levels and scale. Experimental results demonstrate 34 dB analog input dynamic range and 0.7 mW power dissipation at 3 μs cycle
Keywords :
CMOS analogue integrated circuits; VLSI; circuit feedback; vector quantisation; 0.7 mW; 2.0 micron; 3 mus; 4 bit; analog vector quantizer; charge-based distance estimation cells; constant power-decay product; distance metric; double-poly CMOS technology; dynamic template storage; energetic efficiency; input dynamic range; linear complexity; mean absolute difference; power dissipation; winner-take-all output circuit; CMOS technology; Circuits; Concurrent computing; Encoding; Power dissipation; Prototypes; Quantization; Semiconductor device measurement; Vectors; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
