On fault probabilities and yield models for VLSI neural networks

Author

Furth, Paul M. ; Andreou, Andreas G.

Author_Institution

Dept. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA

Volume

32

Issue

8

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

1284

Lastpage

1287

Abstract

We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on the framework suggested by Feltham and Maly and is also applicable to analog or mixed analog/digital VLSI systems

Keywords

CMOS integrated circuits; VLSI; error statistics; fault diagnosis; integrated circuit modelling; integrated circuit yield; mixed analogue-digital integrated circuits; neural chips; neural net architecture; parallel architectures; CMOS technology; VLSI neural networks; fault probabilities; mixed analog/digital VLSI; neural computational models; truly distributed parallel processing systems; yield models; Circuit faults; Computational modeling; Distributed processing; Fault tolerant systems; Neural network hardware; Neural networks; Parallel processing; Silicon; Very large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.604090

Filename

604090