A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

Author

Franch, R.L. ; Ji, J. ; Chen, C.L.

Author_Institution

Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

32

Issue

8

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

1288

Lastpage

1292

Abstract

We describe a 640-ps read access, 16-word by 64-b, three-port register file fabricated in 0.25-μm effective channel length CMOS technology. It features the capability to perform a write followed by a read in the same cycle at frequencies above 500 MHz. High speed is achieved by using a novel cell and array structure. Static circuit design is used exclusively throughout the entire register file and is optimized for high-speed operation. Measured results of the same-cycle read-after-write demonstrate register file operations at 625 MHz. Additionally internal probe measurements of the read access path components are presented and compared with circuit simulations

Keywords

CMOS logic circuits; NAND circuits; circuit analysis computing; circuit feedback; logic CAD; logic arrays; logic gates; multiport networks; shift registers; 0.25 micron; 625 MHz; 64 bit; 640 ps; CMOS; NAND gates; array structure; circuit simulations; feedback inverters; high-speed operation; internal probe measurements; read access path components; same-cycle read-after-write operation; static circuit design; three-port register file; Bandwidth; CMOS technology; Circuit testing; Clocks; Decoding; Hardware; Latches; Microprocessors; Registers; Temperature measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.604091

Filename

604091