A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System

Author

Sunkwon Kim ; Jong-Kwan Woo ; Woo-Yeol Shin ; Gi-Moon Hong ; Hyongmin Lee ; Hyunjoong Lee ; Suhwan Kim

Author_Institution

Dept. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea

Volume

60

Issue

1

fYear

2013

fDate

Jan. 2013

Firstpage

6

Lastpage

10

Abstract

We propose a low-voltage low-power clock and data recovery (CDR) circuit which incorporates a relaxation-based voltage-controlled oscillator and clock-edge modulation, which eliminates the need for an external reference clock without allowing harmonic locking. This CDR supports input data rates between 200 kbps and 10 Mbps at 0.7 V and operates up to 24 MHz at 1.0 V. The proposed design consumes 8 at an input data rate of 10 Mbps and achieves 0.8 pJ/bit of energy per bit even though the circuit is implemented in a 0.18- μm CMOS technology.

Keywords

CMOS integrated circuits; biomedical electronics; brain; clock and data recovery circuits; low-power electronics; voltage-controlled oscillators; CMOS technology; bit rate 200 kbit/s to 10 Mbit/s; clock-edge modulation; external reference clock; frequency 24 MHz; optically controlled neural interface system; power 8 muW; referenceless clock and data recovery circuit; relaxation-based voltage-controlled oscillator; size 0.18 mum; voltage 0.7 V; voltage 1 V; Biomedical optical imaging; Clocks; Optical crosstalk; Phase frequency detector; Voltage control; Voltage-controlled oscillators; Clock and data recovery (CDR); clock-edge modulation (CEM); neural interface; referenceless CDR; relaxation oscillator;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2012.2234872

Filename

6413187