Title :
A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes
Author :
Hamada, Mitsuru ; Fujiwara, Eiji
Author_Institution :
Graduate Sch. of Inf. Syst., Univ. of Electro-Commun., Tokyo, Japan
fDate :
1/1/1997 12:00:00 AM
Abstract :
A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b⩾2, and more efficient than previously known codes with as strong error control capabilities
Keywords :
error correction codes; memory architecture; semiconductor storage; b-bit-per-chip; byte organized memory systems; error control codes; semiconductor memory systems; single byte error correcting; single byte plus single bit error detecting codes; Computer errors; Error correction; Error correction codes; Hamming weight; Linear code; Protection; Redundancy; Semiconductor memory;
Journal_Title :
Computers, IEEE Transactions on
