DocumentCode
1346512
Title
A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes
Author
Hamada, Mitsuru ; Fujiwara, Eiji
Author_Institution
Graduate Sch. of Inf. Syst., Univ. of Electro-Commun., Tokyo, Japan
Volume
46
Issue
1
fYear
1997
fDate
1/1/1997 12:00:00 AM
Firstpage
105
Lastpage
109
Abstract
A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b⩾2, and more efficient than previously known codes with as strong error control capabilities
Keywords
error correction codes; memory architecture; semiconductor storage; b-bit-per-chip; byte organized memory systems; error control codes; semiconductor memory systems; single byte error correcting; single byte plus single bit error detecting codes; Computer errors; Error correction; Error correction codes; Hamming weight; Linear code; Protection; Redundancy; Semiconductor memory;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.559809
Filename
559809
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