DocumentCode :
1346679
Title :
Effect Of Device Reliability On Memory Reliability
Author :
Humphry, Jonathan A.
Author_Institution :
Del Rey Systems, Inc., 8327 Pershing Drive; Playa del Rey, California 90291 USA.
Issue :
5
fYear :
1980
Firstpage :
416
Lastpage :
421
Abstract :
Two important factors in the design of a memory for a computer with a long life expectancy are: the reliability of the parts comprising the system and type of reliability enhancement technique selected. The most significant conclusion of this paper is that memory system reliability is extremely sensitive to memory IC failure rate, ¿. For the memory system example, ¿ must be approximately 10-7 failures/hour for the system to have a useful life expectancy. If ¿ is appreciably less than 10-7 then little or no protection is required to achieve the design goals. On the other hand, if the failure rate is appreciably greater than 10-7, then the design goals cannot be achieved no matter which technique is selected. Apparently, the underlying factor is the reliability per function. This quantity improves as the level of integration increases since chip reliability is relatively insensitive to chip density.
Keywords :
Central Processing Unit; Fault tolerance; Fault tolerant systems; Large scale integration; Military computing; NASA; Probability; Protection; Redundancy; Reliability; Bit rippling; Fault tolerant memory; Recovery software; Reliability enhancement techniques; Reliability model; SEC/DED code;
fLanguage :
English
Journal_Title :
Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9529
Type :
jour
DOI :
10.1109/TR.1980.5220906
Filename :
5220906
Link To Document :
بازگشت