Author :
Bergmans, J.W.M. ; Voorman, J.O. ; Groenewold, G. ; Hollmann, H.D.L. ; de Jong, G.W. ; Lugthart, M.L. ; Pothast, J. ; Ramaekers, J.A.M. ; Ramalho, J.N.V. ; Van Riel, L.F.H. ; Veenstra, H. ; Wong-Lam, H.W. ; Medley, D.H. ; Bhandari, S. ; Dakshinamurthy, R.
Abstract :
The channel IC described here achieves data rates of 380 Mb/s at performance levels that improve in various directions upon the state of the art. It accomplishes these feats in a mature 1 μm CBiCMOS technology at a readmode power consumption of only 800 mW. The paper discusses some of the underlying architectural concepts
Keywords :
BiCMOS integrated circuits; decision feedback equalisers; hard discs; mixed analogue-digital integrated circuits; 1 micron; 300 Mbit/s; 800 mW; CBiCMOS technology; architectural concepts; data rates; dual-DFE read/write channel IC; hard-disk drives; readmode power consumption; Bandwidth; Circuit noise; Clocks; Ear; Energy consumption; Frequency synthesizers; Hard disks; Modulation coding; Random sequences; Semiconductor device noise;
