A 3.3-V/5-V low power TTL-to-CMOS input buffer

Author

Wang, Chi-Chang ; Wu, Jiin-Chuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

33

Issue

4

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

598

Lastpage

603

Abstract

A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applications. It has low power dissipation, high operating speed, and a logic threshold voltage less sensitive to process and supply voltage variations. The proposed SSIB input buffer was realized in a 0.8-μm single-polysilicon double-metal (SPDM) CMOS technology, The measured logic threshold voltage variations due to process variations are ±24 mV for 5 V supply and ±16 mV for 3.3 V supply, respectively. Its logic threshold voltage variations due to supply voltage variation from 3.3 V to 5 V are within 10 mV. In ring oscillator configuration, the measured delay and power dissipation are 0.45 ns and 0.37 mW for 5-V supply and 0.51 ns and 0.14 mW for 3.3-V supply, respectively

Keywords

CMOS logic circuits; buffer circuits; delays; logic gates; transistor-transistor logic; 0.14 mW; 0.37 mW; 0.45 ns; 0.51 ns; 0.8 micron; 3.3 V; 5 V; SSIB input buffer; TTL-to-CMOS input buffer; delay; dual voltage applications; logic threshold voltage; operating speed; power dissipation; ring oscillator configuration; self-biased circuit; single-polysilicon double-metal technology; CMOS logic circuits; CMOS technology; Inverters; MOS devices; Power dissipation; Power measurement; Ring oscillators; Threshold voltage; Very large scale integration; Voltage measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.663565

Filename

663565