Low-latency distance protective relay on FPGA

The need for high-speed multi-function protective relays in both traditional transmission systems and the new emerging paradigm of the smart grid is growing. As a widely used protective scheme for transmission lines, a distance relay´s high speed and reliable operation to clear faults is essential. This paper proposes a real-time low-latency hardware digital distance protective relay on the field programmable gate array (FPGA). Taking advantage of inherent hard-wired architecture of the FPGA, the proposed hardware distance relay design is paralleled and fully pipelined to achieve low latencies in various relay modules which are developed in textual VHDL language. This low-latency feature allows fast operating and data throughput so that the relay can handle high-frequency sampled data and reach higher computational efficiency. In addition, the parallelism and hardwired architecture of the FPGA makes the design more reliable in computation than the sequential software-based numeric relay. The FPGA-based distance relay can operate on both phasor-based signals and instantaneous signals with 2.09 microseconds and 0.35 microseconds latency respectively based on the clock frequency of 100 MHz. The hardware relay is tested in real-time by feeding it with generated faulted current and voltage data for typical faults and the relay response recorded. The results demonstrate the speed and effectiveness of the hardware distance relay.